Current limiting protective means

ABSTRACT

A high-speed AC electric power switch and current-limiting impedance combination suitable for interconnecting a static inverter and its load circuit is arranged to respond to an overload condition by inserting the impedance in series with the load so fast that the inverter can remain in service with its integrity unimpaired. The switch is also arranged to subsequently isolate the load circuit from the inverter in the event that the overload condition has not otherwise been relieved within a predetermined length of time.   D R A W I N G

United States Patent Inventor Allan N. Greenwood Media, Pa.

Appl. No 733,150

Filed May 29, 1968 Patented Jan. 26, I971 Assignee General ElectricCompany a corporation of New York CURRENT LIMITING PROTECTIVE MEANS 12Claims, 2 Drawing Figs.

US. Cl 317/20, 317/23, 317/33, 321/14, 323/24 Int. Cl H02h 3/08, H02h 7/14 Field of Search 323/24,

(Inquired); 317/23, 11, 33SCR, 20, (lnquired); 321/14, (Inquired)sol/Rab CHARG/IVG MEAMS CONTROLS [5 6] References Cited UNITED STATESPATENTS 3,098,949 7/1963 Goldberg 307/252X 3,369,154 2/1968 Swain317/33X 3,401,303 9/1968 Walker 317/11 Primary ExaminerJames D. TrammellAtt0rneys-J. Wesley Haubner, Albert S. Richardson, Jr.,

Barry Stein, Frank L. Neuhauser, Oscar B. Waddell and Joseph B. FormanABSTRACT: A high-speed AC electric power switch and current-limitingimpedance combination suitable for interconnecting a static inverter andits load circuit is arranged to respond to an overload condition byinserting the impedance in series with the load so fast that theinverter can remain in service with its integrity unimpaired. The switchis also arranged to subsequently isolate the load circuit from theinverter in the event that the overload condition has not otherwise beenrelieved within a predetermined length of time.

LOAD

PATENTEUJANZSISYI 3.558.982

SHEEE 2 [IF 2 DELAY DETECTOR INVENTOR ALLAN GREENWOOD,

5y GIL-a5, ATTORNEY CURRENT LIMITINGPROTECTIVE MEANS thereby, so thatcritical loads can continue operating with theleast possibledisturbance. Reliable power can be essential for loads suchas'computers, for example, where even a transient dip in voltage, or amomentary loss of power, can result in serious errors or malfunctions inthe utilizationequipment and an extendedoutage could beintolerable.Consequently, to improve the quality and continuity ofelectricity supplied to such loads, electrical manufacturers have madeavailable uninterruptible power systemsjfson etim es referred to asno-break power supplies, for installation between the incoming powerlines and the load. Such apparatus typically comprises one or morecombinations of rectifying, energy storing, and inverting 1 sections soarranged as to faithfully energize a critical bus with highly stable ACpower regardless of disturbances in, or failure of, utility power.

In practice a plurality of load or feeder circuits are often connectedin parallel to a common criticalbus, and such feeders include suitableprotective devices (e.g.,'fuses) for'au tomatically isolating anindividual feedercircuit in the event of a fault involving solely thatbranch of the system. During the period of time normally required toisolate'or clear such a fault selectively, it is important to preservethe integrity of the inverter so that whenthe branch fault is clearedthe critical damage is caused to the apparatus.v Accordingly, my generalobjective is to provide improved protective means for accomplishingthese ends.

'A further objective of my invention is the provision, for a controlsdescribed but not claimed herein are the invention of F. L. Steen, forwhich see his copcnding patent application Ser. No.= 738,6ll, filed onJune 20, I968, assigned to the General Electric Company. v

The switch illustrated in FIG. I is adapted to'be serially connected ina load current conducting path 41 between an electric power source and aload circuit. In a three-wire, threephase AC system, a total of threeduplicate switches would be used in practice, all three sharing commoncontrols 80.

The load circuit typically comprisesa bus having a plurality ofseparately protected feeder circuits or branches (not shown).Alternatively, the source could be a power distribution bus; and theload circuit a feeder individually protected bymy switch. Thus theswitch is useful'in a variety of settings, and it isparticularlyadvantageous in an uninterruptible power system such as theone referred to briefly in the introduction of this specificationand'explained more fully in copending U.S. application Ser. No. 733,446filed on May 3 l, 1968, U.S.

Pat. No."3,530,360 for A. E. Relation and assigned to the GeneralElectric Company.

In the'switch there is a main circuit 50 comprising load currentconducting solid-state-controlled switching means, and the'main circuitis shunted by a subsidiary circuit 60 comprising'the combination ofanother switching means in series with current limiting impedance means61. The solid-state-controlled'switchingm'eans of the main circuit 50 isnormally maintained in a' relatively low resistance, turned-on state,whereby load current 'can easily traverse the switch. Preferably thisswitching means comprises first and second semiconductor controlledrectifie rs 51v and 52 disposed in inverse parallel relationship withone another as shown. Such devices are known generally asthyristors, andmore information about them can be obtained from published literaturesuch as the reference book SEMICONDUCTOR CON- TROLLED RECTIFIERS by F.E. Gentry et al. (Prentice-Hall Inc. Englewood Cliffs, N.J., I964). Themain thyristors SI and 52 are turned on (triggered) by means of suitablefiring signals s pplied theretofrom-the associated controls 80 viaconnecvariety of useful purposes, ofiprotective means characterizedxsecondpair of inverse parallel, relatively light-duty thyristors.

Commutating meansis providedfor high-speed turnoff of the first pair ofthyristors when a slight oyerload is detected, whereupon throughcurrentis forced to traverse the currentlimiting resistor whi ch limitsits .rnagnitude while preserving service continuity. v A. short timelater the second pair of thyristors is turned off by discontinuing theirfiring signals to open the circuit completelyunless the overload haspreviously subsided (due, for example, to the blowing of branch fuses).

My invention will be better understood and its various objects andadvantages will be more fully appreciated from the following descriptiontaken in conjunction v with the accompanying drawings inwhich:

tionsS lg and 523, respectively. I

If desired for higher current and voltage ratings of the switch,duplicate devices can be connected in parallel and series and operatedin unison with the thyristors 51 and 51, respectively. The mainthyristors are selected to safely conduct their respective shares offull load current continuously.

Preferably the main circuit 50 of the switch also includes'a 1 pair ofdecoupling inductors 53 and 54 which are respectively comprises'a'pair'of thyristors 63 and 64 connected in inverse FIG. 1 is a schematicdiagram ofa single-phase version of my improved protective means; and

FIG. 2 is a functional block diagram of apreferred embodiment of thecontrols shown as a single bl'oclt in FIG. 1.

In F IG. 1 the power circuit of the protective means has been showninside a broken-line box labeled switch," and the associated controlsare shown generally asa block 80. Further details ofthe controls areillustrated in FIG. 2 which ,will be described later. Certain novelfeatures of the switch and its minedlimited length of time (see below),they can have an appreciably lower thermalrating (and hence smaller sizeand lower cost) than the thyristors in the main circuit 50.

Preferably the resistance value of the resistor 61 is selected to limitthe current that can traverse the'switch, when the main thyristorsSI and52 are both turned'off and when the whole load is short circuited, to amagnitude approximately equal to percent normal full load'current.

To sense the'magnitude of current in the load current path 41', theillustrated switchincludes a current transformer 55 which supplies aproportional'input signal to the controls 80.

The controls are designed to initiate an extremely fast transfer ofthrough current from the maincircuit 50' to the subsidiary circuit 60 inimmediate response'to the occurrence of-any condition that causesabnormally high current in the main circuit, as reflected by the currenttransformer 55. lfthe resulting transfer is quick enough, the resistor61 can impede any apprecia'ble rise in current above the pickup leveland will in fact limit current to its 100 percent value, whereby thesupply apparatus (e.g., a static inverter) can continue operatingwithout shutdown'or'damage and servicecontinuity is at least temporarilypreserved.

in order to accomplish this result, the switch includes means, operativewhen commanded bythe controls 80, for immediately forcing the mainthyristors 51, 52 to change abruptly from their low resistance,turned-on states to high resistance, tumed-off states. Such actionrequires that anode current in any conducting .thyristor be quenched andits firing signal be discontinued (suppressed) without waiting for thenext natural current zero. To quench current in a conducting thyristor,suitable commutating means is connected to the main thyristors 51 and52.

The commutating means, which can take a variety of forms well known inthe art, preferably comprises firstand second capacitor-thyristorcircuits respectively connected in parallel with the main thyristors 51and 52 to divert current from the latter when the correspondingcommutating thyristor is triggered, whereby both of the main thyristorscan immediately assume a high resistance, essentially nonconductingstate. Thus, as is clearly shown in FIG. 1, the series combination of apower capacitor 71, a commutating thyristor-73, and a small reactor 75is connected across the main thyristor 51, and. a similar combination ofa power capacitor 72 in series with a commutating thyristor 74 and asmall reactor 76 is connected across the'main thyristor 52. Inaccordance with the teachings of U.S. Pat. No. 3,098,949 to Goldberg,each of the power capacitors 71 and 72 is precharged to a suitable DClevel by suitable charging means 77 which is energized by source voltageV The relative polarity of the charge on each capacitor has beenindicated on FIG. 1. The commutating thyristors 73 and 74 are triggeredby firing signals supplied thereto from the controls 80 via connections73g and 74g, respectively.

Althoughomitted in the drawings, it will be understood the conventionalsnubber circuits would ordinarily be connected in parallelwith each ofthe thyristors shown in FIG. 1 to limit the rate of voltage rise acrossthe thyristor when turning off.

Before proceeding with a description of FIG. 2, the various operatingmodes of the switch shown in FIG. 1 will now be summarized. Normally thethyristors 51,52 in the main circuit .50 are turned on and alternatingcurrent freely traverses the same. The controls 80 are arrangedtorespond immediately to a condition of abnormally high current in theswitch by supplying firing pulses to the commutating thyristors 73, 74.As a result, overcurrent is commutated from whichever main thyristor wasconducting to the power capacitor in parallel therewith, and both of themain thyristors $1, 52 are-quickly turned ofi". Substantiallysimultaneously the firing signals for the main thyristors aresuppressed, which can be done either in automatic response to thecommutating action or, as disclosed herein, by suitably programming thecontrols 80. At the same time the switching means 62 in the subsidiarycircuit is turned on, whereby the current-limiting resistor 61 iseffectively connected in parallel with the main circuit 50. As soon asthe capacitor in the commutating circuit discharges and current throughthe commutating thyristor oscillates to zero, the latter reverts to itshigh resistance, tumed-off state and current, flowing through theswitch, is forcedto traverse the current-limiting resistor 61. The timerequired to detect the overcurrent condition and to complete theimpedance inserting action is measured in microseconds.

The controls 80 are also arranged to suppress the firing signals for theswitching means 62 in series with the current limiting resistor 61 inresponse to the abnormally high current condition continuing for apredetermined length of time (e.g., 3 seconds), thereby causing theswitching means 62 to turn off and interrupt current. through theresistor 61-. Consequently the load circuit can bec'omplctely isolatedfrom the power source. However, if prior to the expiration of thisinterval of time a downstream fuse blows, or the fault is otherwisecleared, so that the abnormally high current condition terminates, theswitch will automatically return to its normal state. Termination of theabnormal condition is indicated by current in the load path 41 subsidingto a predetermined drop-out value which may, for example, be 50 percentof the pickup level. This subsidence of current is sensed by currenttransformer 55, and the controls respond thereto by restoring thefiring-signals for the .main thyristors 51 and 52 which can then resumetheir nonnal low resistance, turned on states.

As will soon be explained in greater detail, the controls 80 arepreferably arranged simultaneously to trigger the commutating thyristor73, 74 and'to suppress the firing signals for both the main thyristors51, 52 and the switching means'62 in high-speed response to thereceipt-of an extemally-imposed tripping signal indicated symbolicallyin FIG. 1 by. the encircled T. Alternatively, the controls 80 willsuppress the firing signals for the main thyristors 51, 52, and will nottrigger any of the other thyristors in response to a predetermined offcommand. 1

In order to restart orreclose a turnoff switch, switching means 62 isfirst triggered, thereby inserting the resistor 61 in series with theload current path 41, and subsequently the main thyristors 51 and 52are'triggered into their conducting states. This operating sequenceserves several useful purposes. While the resistor 61 is effective, itlimits the magnitude of inrush current to the load circuit,therebyproviding a soft start and avoiding unnecessary opening of theswitch in response to only a transient overcurrent condition. The delayin triggering the main thyristors 51,52 provides time for prechargingthe commutating capacitor 71 and 72, and if there is a preexisting loadfault the firing signals for the main thyristors will remain suppressed.

Turning now to FIG. 2, there is shown a functional block diagram ofcontrol details that can be used in practicing my invention. In FIG. 2the blocks 81, 82, and 83, which are labeled Zf main, and com,"respectively, represent firing signal generators for triggering theswitching means 62, the main thyristors 51, 52, and the commutatingthyristors 73, 74 of the switch shown in FIG. 1. The internal circuitsof the respective generators 81,82, and 83 can be conventional (e.g.,see chapters 5 and 7 of the above-cited Gentry et al. reference book),and there is therefore no need to disclose them in detail herein.

The generator 83 is operative to produce one short (e.g., 20mircoseconds) pulselike firing signal for each of'the commutatingthyristors 73,- 74 when triggered by an impedance inserting command fora from an overcurrent detector 84. The input signal-to the detector 84,which is noted in FIG. 2 as i,, and is derived from the previouslymentioned current transformer 55, is proportional to the value ofcurrent'actually flowing through the FIG. 1 switch. In a' three-phaseapplication, the detector would additionally be supplied withcorresponding inputs from the other two phases. In either case thedetector 84 is designed to'produce an output signal 85 in substantiallyinstantaneous response to any input signal attaining a preset pickuplevel which represents'a predetermined value of overcurrent in the loadcircuit supplied by the switch ;(e.g., I25 percent rated full loadcurrent). The detector 84 will then sustain its output signal 85 untilload current subsequently subsides to another,.lower predetermined value(e.g., 50 percent of the pickup value), whereupon the impedanceinserting command terminates. The leading edgc of the signal 85 triggersthe firing signal generator 83.

Alternatively, the generator 83 may be activated by an opening commandin the form of an externally imposed tripping signal 86. Therefore thetwo signals 85 and 86 are fed to the generator 83 via a conventional ORlogic circuit 87. The generator 83 will produce firing signals forsubstantially simultaneously turning on both commutating thyristors 73,74

in highspee dresponse.to the issuanceof either command.

' Turning on the commutating thyristors immediately commugenerator 83.

The main firing signalgenerator 82 is operative when enabled to producesuitable firing signals for. triggering both of the main thyristors 51and 52.=Itis controlled by logic means 4 so arranged that the generator.82 is normally enabled, whereby the main thyristors 51 and 52 arenormally maintained in their turned onstat es. The logic symbol shown at88 represents an AND function having two NOT inputs-88a and 88b. So longas there isno signal applied to .either of these inputs, the logiccomponent 88 .will provide an o'utputsignal 89 that enables thegenerator 82 to operate. The output signal 89 is sup-.

pressed, thereby disabling the generator 82 and, consequentlysuppressing the firingsignals for the mainthyristors 51, 52, inimmediate response to an input signal at either 88a or 88b.

.The input 88afor the logic component-88is energized by the 98b. Unlessa signal is applied to the first input 98a and none to the second input98b,- no output signal 99 is provided by the component 98 and operationof the generator 81 is prevented or blocked.- n

The input 98a'for the logiccomponent 98 is energized via an OR-logiccircuit 100 by the output signal 85"fr om the over current detector 84,whereby the generator 81 is activated and starts triggering theswitching means 62 at the same time the commutating thyris tors 73 and74 are triggered by the impedance inserting command. Alternatively, theinput 98a may be energizedby a signal 102 that is produced by a logiccomponent 101 on' receipt of a switch-closing command from meansindicated by the legend on. In any event, the output signal 99 of thelogic component 98 is suppressed. thereby afresponse to' issuance? of anopeningcommand corresponding output signal 85 from the overcurrentdetector 84, whereby the generator 82 stops ,triggering-themainthyristors at the same time the commutating thyristors are triggered bythe imtothe'appearance of either the output signal 95 of the timingcircuit 94 (indicatingthat the impedance inserting command hascontinuedto'subsist for at least 3 seconds) or the tripping signal86.-When none .of the thyristors is triggered, the switch is in its opencircuit condition;

To close the switch, a closing command is issued to the 1 ANDcomponentlOl which immediately produces the signal pedance insertingcommand. The. generator 82 will remain disabled and the mainthyristorsSl, 52-will remain off so long 1 as the signal 85 subsists. 1

Theother input88 bifor thecomponent 88, is energized by a signal 91 thatis produced whenever anyoneof a plurality of alternative input pulses issupplied to an OR unit 90. ln ac-. cordance with the above-citedSteenJapplieation, once the signal 9Lappears it is maintained until thecontrols 80 are subsequently reset deliberate closing command. In FIG.-2thislatchingfun ction is shownsymbolicallyby angOR component 92 and anAND component 93. When the :unit 90 receives an input pulse the ANDcomponent93 produces the signal 91 and seals itself in until'subsequently released by energization of its NOT input 93a, 1 7

Four fpo s sibleinputs to the OR unit 90 are indicated in FIG. 2. One?is derived in delayed response to the operation of the overcurrentdetector84 by means of a timingcircuit 94.-The

timing circuit 94 is designed to produce an output signal 95 i whenactivated continuously by thesignal85 for a predetermined length of time(e.g. 3 seconds). The delayed signal 95 1.

causes the second disabling signal .91 to appear, after which the maingenerator 82 will rernain disabledeven though the signal 85 isdiscontinued. It will now be apparent that whenevertheoverload.conditionterminates,before the aforesaid time interval6XpII6 S lZ )Ol1h the overcurrent detector 84 and the timing circuit 94will immediately reset and no signal 95 will 1 be produced, and inresponse tothe termination of the overcurrent signal 85, the enablingsignal89, automatically returns to enable the gen'erator82 to resumetriggering the main thyristors sl, 52.1.

Other inputs for the OR, unit 9 are derived from the tripping signal 86or from manually operated means' indicated by thel'egend :fof ffforfromany desired automatic inhibiting condition that results in asignalbeing applied ,to a terminal The block 81 in FIQ. '2 represents.suitable means for controlling the conductive state of theswitching-means 62 that is connectedin series withthe current limitingresistor 61 of the FIG. l,switch. The ,means 8l is operative when activeto produce an appropriate signal for turningon or closing the switchingnieansQWher inverse parallel thyristors 63 and 64 are used, itcancomprisea,tiring signalgenerator similar to the one shown at 82fttriggering the main ,thyristors. The

generator 81 is itselfcontrolledby logic means 5 preferably arranged torender. itnor' mallyinactive, whereby the subsidiary thyristors63 and64arenormally maintained in their turned off states. This isaceomplishedby means ofthe AND logic component 98 having one regularinput 98a one NOT input l02 and latches in as is indicated symbolicallyat 103 in FIG. 2. T he signal =l02'unblocks thefiring signal generator81 which starts triggering the switching ,means 62 in series with thecurrent :limiting resistor 61 in the subsidiary circuit 60 ofthezswitch. Simultaneously it activates a timing circuit 104 which ashort time later (e.g., 0.2 second) produces an output signal 105.Thesignal-105 energizes the NOT input 930 of the logic component 93 torelease or unlatch the latter, whereupon'the signal 9l't erminates,thesignal 89 reappears, and the main firing signal generator 82 is againenabled. This causes the main thyristors 51, 52 to turn on andclose""the low resistance main circuit 50 of the switch. At the sametime, by

meansof aconn'ection from the output of the timing circuit through theOR circuit 106 to the NOT input 101a of the component l0l.'Theadvantages of the closing sequence outline in this paragraphwerepreviously explained. I

While the presently preferred form of my invention has been shownanddescribed by way of illustration, many modifications will occur to thoseskilled in the art. I therefore con-' template by the claims whichconclude this specification to cover all such modifications as fallwithin the true spirit and scope ofmy invention;

Iclaim: I

1. Over-current protective'means comprising:

a. a main circuit'co mprising solid-state-controlled switching meanswhich is normally maintained in a relatively low resistancestatewhereby'electric current can easily traverse said main circuit;

b. means for serially connecting said main circuit in a load currentconducting path between a source of electric power and an electric powerload circuit; I

c. said maincircuitbeing shunted by the combination of another switchingmeans in series with load current limiting impedance means:

d. means operative in immediate response to a condition ofabnormally-high current in said path for causing said controlledswitching means to change from its low resistance, turned on state to ahigh resistance, turned-off state, whereupon load current is forced totraverse said impedance means; and

e. means operative in'delayed response to said abnormally high currentcondition for causing said other switching means to turn off, therebyinterrupting current through connected in inverse said impedance means,.unless said abnormal conditionhas earlier terminated. I 2. Theprotective means of claim 1 including means for causing said controlledswitching means to resume its normal low resistance state in response tothe termination of said abnormal condition prior to the operation of themeans for turning off said other switching means.

3. The protective means of claim 1 in which the means for turning offsaid controlled switching means comprises commutating means forquenching current in said controlled switching meansin high-speedresponse-to the occurrence of said abnormally high-current condition.

4. The protective means of claim 3 in which said other switching meanscomprises additional solid-state-controlled switching means which isturned on by the operation of an associated firing signal generator whensaid first-mentioned controlled switching means is turned off, and inwhich the means for turning off said other switching means comprisesmeans for deactivating said generator in response to said abnormallyhigh-current condition continuing for a predetermined length of time.

5. The protective means of claim 1 in which said path conductsalternating current and both of said switching means cxsistance,turned-on state, whereby electric'current can easily traverse said maincircuit;

b. means for serially connecting said main circuit in a load currentconducting path betweena source of electric' power and an electric powerload circuit; a c. said main .circuit being shunted by the combinationof another switching means in series with loadcurrent limiting impedancemeans;

d. commutating means operative in high-speed response to a first commandfor quenching current in said controlledsWitching means, whereupon saidcontrolled switching means abruptly changes from itslow resistance stateto a high resistance, tumed-off state which forces current to traversesaid impedance means; and e. means operative in response to a secondcommand issued I after said first command for causing said otherswitching means to turn off, thereby interrupting current through saidimpedance means.

9. In combination:

.a. a main circuit comprising first solid-state-controlled switchingmeans;

b. first control means operative when enabled for triggering said firstswitching means which'consequently can assume a relatively lowresistance, tumed-onstate whereby elec- I tric current can easilytraverse said main circuit;

c. said main circuit shunted by the combination of secondsolid-state-controlled switching means in series with current-limitingimpedance means;

d. second control means operative when activated for triggering saidsecond switching means which consequently can amume a relatively-lowresistance, turned'on state,

thereby effectively connecting said impedance means in parallel withsaid main circuit; e. means for serially connecting said main circuit ina load current conducting path between a source of electric sequentlyenabling said first control means; g. commutatrng means operativequenching current in said first switching means which consequently canassume a high resistance, turned-off state; and I h. means responsive toan impedance-inserting command for substantially-simultaneously:

i. triggering said com'mutating means; ii. activating said secondcontrol means; and iii. disabling said first control means.

10. Overcurrent protective means comprising:

a. a main circuit comprising solid-state-controlled switching meanswhich is normally maintained in a relatively low' resistance statewhereby electric current can easily traverse said main circuit;

b. means for serially connecting said main circuit in a load currentconducting 'path between a source of electric power and an electricpower load circuit;

c. said main circuit being shunted by the combination of anotherswitching means in series with load current-limiting impedance means;and

d. commutating means connected to said controlled switching means forcausing said controlled switching means to change from itslow resistancestate to a high resistance, essentially nonconductive state, inhigh-speed response to the occurrence of an abnormally high-currentcondition, whereupon load current is forced to traverse said impedancemeans.

1 1. In combination:

a. a main circuit comprising first solid-state-controlled switchingmeans;

b. first control means operative when enabled for triggering said firstswitching means which' consequently can assume a relatively lowresistance, turned-on state whereby electric current can easily traversesaid main'circuit;

c. said main circuit being shunted by the combination of secondsolid-state-controlled controlled switching means in series withcurrent-limiting impedance means;

d. second control means operative when activated for triggering saidsecond switching means which consequently can assume a relatively lowresistance, turned-on state, thereby effectively connectingsaidimpedance means in parallel with said main circuit;

e. means for serially connecting said main circuit in a load currentconducting path between a source of electric power and an electric powerload circuit;

- f. means responsive to a closing command for immediately activatingsaid second control means and for subsequently enabling said firstcontrol means;

g. commutating" means operative when triggered for quenching current insaid first switching means which consequently can assume a highresistance, turned-off state; and t h. means responsive to animpedance-inserting command for substantially simultaneously triggeringsaid commutating means and disabling said first control means, saidlast-mentioned meansbeing arranged to enable said first control means toresume triggering said first switching means in response to thetermination of said impedanceinserting command.

12. The combination set forth in claim 11 including means responsive toan opening command issued while said imwhen triggered for

1. Overcurrent protective means comprising: a. a main circuit comprisingsolid-state-controlled switching means which is normally maintained in arelatively low resistance state whereby electric current can easilytraverse said main circuit; b. means for serially connecting said maincircuit in a load current conducting path between a source of electricpower and an electric power load circuit; c. said main circuit beingshunted by the combination of another switching means in series withload current limiting impedance means; d. means operative in immediateresponse to a condition of abnormally high current in said path forcausing said controlled switching means to change from its lowresistance, turned on state to a high resistance, turned-off state,whereupon load current is forced to traverse said impedance means; ande. means operative in delayed response to said abnormally high currentcondition for causing said other switching means to turn off, therebyinterrupting current through said impedance means, unless said abnormalcondition has earlier terminated.
 2. The protective means of claim 1including means for causing said controlled switching means to resumeits normal low resistance state in response to the termination of saidabnormal condition prior to the operation of the means for turning offsaid other switching means.
 3. The protective means of claim 1 in whichthe means for turning off said controlled switching means comprisescommutating means for quenching current in said controlled switchingmeans in high-speed response to the occurrence of said abnormallyhighcurrent condition.
 2. The protective means of claim 1 includingmeans for causing said controlled switching means to resume its normallow resistance state in response to the termination of said abnormalcondition prior to the operation of the means for turning off said otherswitching means.
 3. The protective means of claim 1 in which the meansfor turning off said controlled switching means comprises commutatingmeans for quenching current in said controlled switching means inhigh-speed response to the occurrence of said abnormally high-currentcondition.
 4. The protective means of claim 3 in which said otherswitching means comprises additional solid-state-controlled switchingmeans which is turned on by the operation of an associated firing signalgenerator when said first-mentioned controlled switching means is turnedoff, and in which the means for turning off said other switching meanscomprises means for deactivating said generator in response to saidabnormally high-current condition continuing for a predetermined lengthof time.
 5. The protective means of claim 1 in which said path conductsalternating current and both of said switching means exhibitbidirectional conducting capabilities.
 6. The protective means of claim5 in which said solid-state control switching means comprises a pair ofthyristors connected in inverse parallel relationship with one another.7. The protective means of claim 6 in which said other switching meanscomprises an additional pair of thyristors connected in inverse parallelrelationship with one another.
 8. In combination: a. a main circuitcomprising solid-state-controlled switching means which is normallymaintained in a relatively low resistance, turned-on state, wherebyelectric current can easily traverse said main circuit; b. means forserially connecting said main circuit in a load current conducting pathbetween a source of electric power and an electric power load circuit;c. said main circuit being shunted by the combination of anotherswitching means in series with load current limiting impedance means; d.commutating means operative in high-speed response to a first commandfor quenching current in said controlled switching means, whereupon saidcontrolled switching means abruptly changes from its low resistancestate to a high resistance, turned-off state which forces current totraverse said impedance means; and e. means operative in response to asecond command issued after said first command for causing said otherswitching means to turn off, thereby interrupting current through saidimpedance means.
 9. In combination: a. a main circuit comprising firstsolid-state-controlled switching means; b. first control means operativewhen enabled for triggering said first switching means whichconsequently can assume a relatively low resistance, turned-on statewhereby electric current can easily traverse said main circuit; c. saidmain circuit shunted by the combination of second solid-state-controlledswitching means in series with current-limiting impedance means; d.second control means operative when activated for triggering said secondswitching means which consequently can assume a relatively lowresistance, turned-on state, thereby effectively connecting saidimpedance means in parallel with said main circuit; e. means forserially connecting said main circuit in a load current conducting pathbetween a source of electric power and an electric power load circuit;f. means responsive to a closing command for immediately activating saidsecond control means and for subsequently enabling said first controlmeans; g. commutating means operative when triggered for quenchingcurrent in said first switching means which consequently can assume ahigh resistance, turned-off state; and h. means responsive to animpedance-inserting command for substantially simultaneously: i.triggering said commutating means; ii. activating said second controlmeans; and iii. disabling said first control means.
 10. Overcurrentprotective means comprising: a. a main circuit comprisingsolid-state-controlled switching means which is normally maintained in arelatively low resistance state whereby electric current can easilytraverse said main circuit; b. means for serially connecting said maincircuit in a load current conducting path between a source of electricpower and an electric power load circuit; c. said main circuit beingshunted by the combination of another switching means in series withload current-limiting impedance means; and d. commutating meansconnected to said controlled switching means for causing said controlledswitching means to change from its low resistance state to a highresistance, essentially nonconductive state, in high-speed response tothe occurrence of an abnormally high-current condition, whereupon loadcurrent is forced to traverse said impedance means.
 11. In combination:a. a main circuit comprising first solid-state-controlled switchingmeans; b. first control means operative when enabled for triggering saidfirst switching means which consequently can assume a relatively lowresistance, turned-on state whereby electric current can easily traversesaid main circuit; c. said main circuit being shunted by the combinationof second solid-state-controlled controlled switching means in serieswith current-limiting impedance means; d. second control means operativewhen activated for triggering said second switching means whichconsequently can assume a relatively low resistance, turned-on state,thereby effectively connecting said impedance means in parallel withsaid main circuit; e. means for serially connecting said main circuit ina load current conducting path between a source of electric power and anelectric power load circuit; f. means responsive to a closing commandfor immediately activating said second control means and forsubsequently enabling said first control means; g. commutating meansoperative when triggered for quenching current in said first switchingmeans which consequently can assume a high resistance, turned-off state;and h. means responsive to an impedance-inserting command forsubstantially simultaneously triggering said commutating means anddisabling said first control means, said last-mentioned means beingarranged to enable said first control means to resume triggering saidfirst switching means in response to the termination of saidimpedance-inserting command.
 12. The combination set forth in claim 11including means responsive to an opening command issued while saidimpedance-inserting command subsists for deactivating said secondcontrol means which consequently stops triggering said second switchingmeans.